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  Make command tutorial
  Add Date : 2018-11-21      
  The code into an executable file, called a compiler (compile); to compile, or compile that (ie, build arrangements), is called to build (build).

Make the most commonly used tools to build, was born in 1977, mainly for projects C language. But in fact, any file as long as there is a change, it is necessary to re-build the project, you can use Make constructed.

This article describes the Make command usage from simple talk, without any foundation, just use the command line, you can understand. My main reference is Isaac Schlueter of "Makefile file Guide" and "GNU Make Manual."

A, Make concept

Make this word in English means "production." Make use of this command directly to the meaning, it is to make a file. For example, to make a file a.txt, you can execute the following command.

$ Make a.txt
However, if you really enter this command, it does not work. Because the Make command itself does not know how to make a.txt, need someone to tell it, how to call other commands to accomplish this goal.

For example, assume the file a.txt dependent on b.txt and c.txt, it is a product of the latter two documents connected (cat command). So, make the following rules need to know.

a.txt: b.txt c.txt
    cat b.txt c.txt> a.txt
In other words, make a.txt behind this command is actually divided into two steps: first, to confirm b.txt c.txt must already exist and the second step using the cat command to merge the two files, output as a new file.

Rules like this are written in a file called a Makefile, Make rely on this file command to build. Makefile files can also be written as makefile, or use the command line parameter to specify a different file name.

$ Make -f rules.txt
Or #
$ Make --file = rules.txt
The above code specifies the make command file based rules.txt rules build.

In short, make just a tool to be constructed in accordance with the specified Shell command. Its rules are simple, you specified which file you want to build, it depends on which source files, when those documents are subject to change, how to re-build it.

Two, Makefile file format

Construction rules are written in the Makefile inside, you want to learn how to Make command, you must learn how to write Makefile files.

2.1 Overview

Makefile file consists of a set of rules (rules) composition. Each rule in the form below.

< Target >: < prerequisites >
[Tab] < commands >
The upper part of the first line in front of the colon, called the "target" (target), part of the colon is called "pre-conditions" (prerequisites); the second line must be a tab key First of all, followed by "command" (commands) .

"Target" is required, can not be omitted; "pre-conditions" and "order" are optional, but there must be at least one among the two.

Each rule clearly two things: What is the goal of building the pre-conditions and how to build. Here's a detailed explanation, the three components of each rule.

2.2 Target (target)

A target (target) constitutes a rule. The target is usually a file name, object specified Make command to be built, such as a.txt above. The destination can be a file name, or a multiple filenames, separated by spaces between.

In addition to the file name, the destination can also be a name of an operation, which is called "pseudo-objective" (phony target).

      rm * .o
The above objective of the code is clean, it is not a file name, but the name of an operation, a "pseudo-objective", is to delete the object files.

$ Make clean
However, if the current directory, just have a file named clean, then the command will not be executed. Make find clean because the file already exists, it is not considered necessary to re-build, it will not execute the specified rm command.

To avoid this, you can explicitly declare clean "pseudo-objective", written as follows.

.PHONY: Clean
        rm * .o temp
Declared clean after "pseudo-objective", make will not go to check whether there is a file named clean, but every time you run the corresponding command is executed. .PHONY Like this there are a lot of built-in target name, you can view manuals.

If you do not specify a target Make command is run, the default will execute the first target of the Makefile.

$ Make
The above code is executed the Makefile the first goal.

2.3 Pre-conditions (prerequisites)

Pre-conditions are usually a set of file names, separated by spaces between. It specifies the "target" criteria for judging whether to re-build: as long as there is a pre-file does not exist, or have been updated (last-modification timestamp than the target pre-file a new timestamp), "target" will need to re Construct.

result.txt: source.txt
    cp source.txt result.txt
The above code, build result.txt precondition is source.txt. If the current directory, source.txt already exists, it can make result.txt properly, or you must write a rule to generate source.txt.

    echo "this is the source" > source.txt
The above code, behind source.txt no pre-conditions, it means that it has nothing to do with the other documents, as long as the file does not exist, each call to make source.txt, it will generate.

$ Make result.txt
$ Make result.txt
The above command is executed twice in a row make result.txt. First performance will be New source.txt, then New result.txt. The second execution, Make source.txt found no change (timestamp later than result.txt), it does not do anything, result.txt will not regenerate.

If you need to generate more than one file, often using the following wording.

source: file1 file2 file3
The above code, source is a pseudo-objective, only three pre-file, there is no corresponding command.

$ Make source
After executing the command make source, it will generate a one-time file1, file2, file3 three files. The following wording than a lot easier.

$ Make file1
$ Make file2
$ Make file3
2.4 commands (commands)

Command (commands) shows how to update the target file, one or more lines of Shell commands. It is to build a "target" specific instruction, its operating results usually generate the target file.

There must be a tab key before each command. If you want to use other keys, you can use the built-in variable .RECIPEPREFIX statement.

> Echo Hello, world
The above code uses .RECIPEPREFIX specified, greater than sign (>) replace tab key. Therefore, each line command into a greater-than sign chapeau instead of tab key.

Note that each command executed in a single shell. No inheritance relationship between the Shell.

    export foo = bar
    echo "foo = [$$ foo]"
After the above code is executed (make var-lost), takes a value of less than foo. Because the two lines in two different processes executed. One solution is to write two lines of command on one line, separated by semicolons.

    export foo = bar; echo "foo = [$$ foo]"
Another solution is to add a backslash before the newline.

    export foo = bar; \
    echo "foo = [$$ foo]"
The last method is to add .ONESHELL: command.

    export foo = bar;
    echo "foo = [$$ foo]"
Three Grammatical, Makefile file

Notes 3.1

Pound sign (#) denotes a comment in the Makefile.

# This is a comment
result.txt: source.txt
    # This is a comment
    cp source.txt result.txt # this is a comment
3.2 Echo (echoing)

Under normal circumstances, make prints each command, and then execute, which is called Echo (echoing).

    # This is a test
Implementation of the above rules, you will get the following results.

$ Make test
# This is a test
In front of the @ command, you can turn off the echo.

    @ # This is a test
Now and then execute make test, there will be no output.

Since the build process, we need to know which command is currently being executed, it is usually only echo comments and pure display command preceded by @.

    @ # This is a test
    @echo TODO
3.3 Wildcard

Wildcard (wildcard) to specify a group of qualified filename. Wildcard Bash consistent with Makefile, mainly with an asterisk (*), question mark (?) And [...]. For example, * .o file suffix named o represents all of.

        rm -f * .o
3.4 Pattern Matching

Make command allows for file names, similar match a regular operation, the main character is used to match%. For example, suppose f1.c and f2.c two source files in the current directory, you need to compile them into corresponding object files.

% .o:% .c
Equivalent to the following wording.

f1.o: f1.c
f2.o: f2.c
Use matching character%, it may be a large number of the same type of file, just use a rule to complete the build.

3.5 Variables and assignment operator

Makefile custom variable allows the use of the equal sign.

txt = Hello World
    @echo $ (txt)
The above code, the variable txt equal Hello World. When called, the variable needs to be placed $ () into.

Call Shell variables required before the dollar sign, plus a dollar sign, because the Make command will escape the dollar symbols.

    @echo $$ HOME
Sometimes, the value of the variable may point to another variable.

v1 = $ (v2)
The above code, the variable's value is another variable v1 v2. In this case a problem arises, v1 value in the end when you define the extension (static extension), or extended at runtime (dynamic extension)? If the value of v2 is a dynamic, results of the two expansion mode may vary widely.

In order to solve similar problems, Makefile provides a four assignment operator (=,: =, =, + =?), The difference between them see StackOverflow.

VARIABLE = value
# When performing extended to allow recursive expansion.

VARIABLE: = value
# When defining extensions.

# Only if the variable is empty when setting values.

VARIABLE + = value
# The value of the variable is appended to the tail end.

3.6 Built-in variables (Implicit Variables)

Make command provides a series of built-in variables, for example, $ (CC) point compiler currently in use, $ (MAKE) Make pointing tool currently in use. This is mainly to cross-platform compatibility, built a detailed list of variables, see the manual.

    $ (CC) -o output input.c
3.7 Automatic variables (Automatic Variables)

Make command also provides some automatic variables, their value and the current rules. Mainly in the following.

(1) $ @

$ @ Refers to the current goal is to Make the target command current build. For example, make foo refers to the $ @ foo.

a.txt b.txt:
    touch $ @
Equivalent to the following wording.

    touch a.txt
    touch b.txt
(2) $ <

a.txt: b.txt c.txt
    cp $ <$ @
Equivalent to the following wording.

a.txt: b.txt c.txt
    cp b.txt a.txt
(3) $?

$? Newer than the target refers to all the pre-conditions, a space in between. For example, rule t: p1 p2, where p2 new timestamp t ratio, it refers to $ p2?.

(4) $ ^

$ ^ Refer to all pre-conditions for a space in between. For example, the rules for the t: p1 p2, then refers to $ ^ p1 p2.

(5) $ *

$ * Refers to matching at the matching portion%, like% match f1.txt in f1, $ * says f1.

(6) $ (@ D) and $ (@ F)

$ (@ D) and $ (@ F) point to $ @ directory name and file name. For example, $ @ is src / input.c, then $ (@ D) value of src, $ (@ F) value input.c.

(7) $ (
$ (
List of all automatic variables, see the manual. Here is an example of an automatic variable.

dest /% txt:. src /% txt.
    @ [-d Dest] || mkdir dest
    cp $ <$ @
The above code will txt file src directory, copied to the dest directory. First, determine dest directory exists, if there is no new, then, $
3.8 Analyzing and recycling

Makefile using Bash syntax, judgment and complete the cycle.

ifeq ($ (CC), gcc)
  libs = $ (libs_for_gcc)
  libs = $ (normal_libs)
The above code is judged whether the current compiler gcc, and then specify a different library file.

LIST = one two three
    for i in $ (LIST); do \
        echo $$ i; \

# Equivalent to

    for i in one two three; do \
        echo $ i; \

The results of running the above code.

3.9 Functions

Makefile function can also use the following format.

$ (Function arguments)
Or #
$ {Function arguments}
Makefile provides many built-in functions for calls. Here are a few commonly used built-in functions.

(1) shell function

shell function is used to execute shell commands

srcfiles: = $ (shell echo src / {00..99} .txt)
(2) wildcard function

wildcard function is used in the Makefile, replace Bash wildcards.

srcfiles: = $ (. wildcard src / * txt)
(3) replacement function

Replace function wording is: variable name + colon + substitution rules.

min: $ (OUTPUT: .js = .min.js)
The above code means that the variable OUTPUT .js all replaced .min.js.

Four, Makefile examples

(1) executing a plurality of targets

.PHONY: Cleanall cleanobj cleandiff

cleanall: cleanobj cleandiff
        rm program

        rm * .o

        rm * .diff
The above code can call different goals, different suffix delete files, or you can call a target (cleanall), remove all specified types of files.

(2) C language compiler project

edit: main.o kbd.o command.o display.o
    cc -o edit main.o kbd.o command.o display.o

main.o: main.c defs.h
    cc -c main.c
kbd.o: kbd.c defs.h command.h
    cc -c kbd.c
command.o: command.c defs.h command.h
    cc -c command.c
display.o: display.c defs.h
    cc -c display.c

     rm edit main.o kbd.o command.o display.o

.PHONY: Edit clean
Today, the introduction Make command on here. Next article I will explain how to use Make to build the Node.js project.
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