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  The virtual memory
  Add Date : 2017-08-31      
  What is virtual memory?

First introduce some extract directly on wikipedia.

Virtual memory is a computer system memory management technology. It makes the application thinks it has successive available memory (complete a continuous address space), but in fact, it usually is divided into a plurality of physical memory fragmentation, there are some temporarily stored on an external disk storage is required when data exchange.

For the C language variables, we can use the & operator to obtain its address, since it is a virtual address refers to the address of the virtual.

Virtual address mechanism is not necessary, in a simple microcontroller, compiled code written when physical RAM is required to specify the spatial distribution, there will be no concept of the virtual address, the address refers to a physical address in RAM.

Why do we need virtual memory?

The following is my understanding, there may be an inappropriate place.

Suppose you run a program on the bare metal, then there is no way to re-execute other programs at the same time, the need to introduce the operating system to manage. Once you have the operating system, we might be able to run several different programs, but it may not be able to execute multiple instances of the same program at the same time, because the program uses the same physical address is the same (assuming the old compiler), together running conflict there. Want to run multiple instances of the same program, it seems there are two kinds of programs.

Use a different address to recompile a program, and not before a conflict.
Use the Add address offset other ways to ensure that the use of a different address when running the program.
The first is to allow the compiler to complete, in theory you can, but it will be too much trouble, if I want to run three, four do, it is necessary to compile more than a few times.
Second it is to allow the operating system to complete, should be regarded as the prototype of the virtual memory. After using this mode, the program inside the compiler gives the associated address is not the actual physical address, and be a virtual address.

X86 virtual memory technology


GDT and LDT are introduced into the x86 system in 80286 when, LDT and GDT has a similar structure. LDT is the emergence of multiple processes to use a separate address space and services, typically one process per LDT, and shared memory and kernel memory use GDT. Each program to determine the base address of the descriptor based on, but there is also a limit for each Entry field, just to make space for program access restrictions. But in the 80386 introduced better after paging technology, LDT basically no longer in use.


As the implementation of the current paging virtual memory technique, there must be a better place than the LDT, but their realization of ideas are similar. The operating system maintains a handle for each process, the handle is associated with the relevant data blocks of the conversion process from the virtual to physical address. The handle is in the LDT LDT pointer and length, data block is LDT itself. By paging mode data block is called paging structure, handler is a pointer thereto.

paging structure has 4096 bytes, contains separate entries, different in different modes of the size of each entry. Each entry contains a physical address, you can point to a page frame, can also point to another paging structur, it is the cascade. Points to the first page structure pointer in the CR3 register, then from the linear address to a physical address in the process is an iterative process. Part of the linear address to indicate corresponding entry, if the entry points to another page structure will continue until the point of a page frame address indicates that the conversion is complete, use this last entry as the base linear address the remaining portion of the partial representation shift.

Now devoted tab 32bit mode. 32bit Under each entry 4bytes, each paging structure contains 1024 entries, 10bit need to distinguish each entry. In fact under 32bit mode using Level 2 pageing structure. The first stage is called Page Directory, use 32bit linear address bits 31-22 to distinguish, the second stage called the Page Table, using 32bit linear address bits 21-12 to distinguish, and the rest is just bits 11-0 calculated in 4K page in the offset.

In all linear addresses to physical address translation, CR3, PDPTE, PDT, PTE, etc. are stored in the base address of the next, the linear address is stored in the offset.
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