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For any design of a hardware module, the first step is to first understand the hardware itself, and then start the program software design. And because many of the DM9000 chip content of the document, to drive a good card, take a long time, especially more difficult for the novice, it can refer to the linux kernel code NIC driver, transplanted them to the bare metal program. The following description will ok6410, detailed procedures DM9000 bare-driven program, and complete arp protocol programming.
1. DM9000 hardware interface
Open floor schematic ok6410 can see DM9000 and ok6410 hardware interface, browse through DM9000 documents probably seen some of the more important pin interface, as shown:
Referring again ok6410 core board schematics can clearly know the hardware interface corresponding pins:
SD0 ~ SD15: DATA0 ~ DATA15: XM0DATA0 ~ XM0DATA15
CMD: ADDR2: XM0ADDR2
INT: IRQ_LAN: GPN7
IOR: OEN: XM0OEN
IOW: WEN: XM0WEN
CS: CSN1: XM0CSN1
From the correspondence between some of the above pins, it may be difficult to understand in a controlled manner, which is very different from bare metal and some other programs GPIO module when. In 6410 chip manual search keywords, for beginners, it is difficult to understand the relationship between each pin. But with online information or can know DM9000 interface connected to the control module ROM1, ok6410 not pick ROM. This can clearly know the following relationship
The data bus ROM1: DATA0 ~ DATA15
ADDR2: ROM1 second address bus
IRQ_LAN: interrupt interface
OEN: nOE
WEN: nWE
CSN1: XM0CSn
So read and write DM9000 module is equivalent to the ROM read and write, the key is the CMD pin is ADDR2.
When CMD when 1 DATA0 ~ DATA15 data bus
When CMD is 0:00 DATA0 ~ DATA15 address bus.
Manual can be obtained by ok6410 ROM1 starting address: 0x18000000
2. DM9000 Programming
2.1 Initialization read and write timing
Ok6410 the DM9000 bare-driven design program
By configuring the following registers timing chart
void cs_init ()
{
SROM_BW & = (~ (0xf << 4));
SROM_BW | = (0x1 << 4);
SROM_BC1 = (0 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | (0x2 << 16) | (0x2 << 24) | (0x2 << 28) ;
}
2.2 read and write functions
#define DM_ADD (* ((volatile unsigned short *) 0x18000000))
#define DM_DAT (* ((volatile unsigned short *) 0x18000004))
void dm9000_reg_write (u16 reg, u16 data)
{
DM_ADD = reg;
DM_DAT = data;
}
u8 dm9000_reg_read (u16 reg)
{
DM_ADD = reg;
return DM_DAT;
}
Analysis shows that the hardware interface that is second CMD ROM1 address bus, a data bus is 1:00, is 0 for the address bus, which can read and write the macro definition.
2.3 DM9000 initialization
DM9000 reference linux kernel driver, you can clearly understand the specific steps to initialize
void dm9000_reset ()
{
dm9000_reg_write (DM9000_GPCR, GPCR_GPIO0_OUT);
dm9000_reg_write (DM9000_GPR, 0);
dm9000_reg_write (DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
dm9000_reg_write (DM9000_NCR, 0);
dm9000_reg_write (DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
dm9000_reg_write (DM9000_NCR, 0);
}
void dm9000_probe (void)
{
u32 id_val;
id_val = dm9000_reg_read (DM9000_VIDL);
id_val | = dm9000_reg_read (DM9000_VIDH) << 8;
id_val | = dm9000_reg_read (DM9000_PIDL) << 16;
id_val | = dm9000_reg_read (DM9000_PIDH) << 24;
if (id_val == DM9000_ID)
{
printf ( "dm9000 is found n!");
return;
}
else
{
printf ( "dm9000 is not found n!");
return;
}
}
void dm9000_init ()
{
u32 i;
// Set chip select
cs_init ();
// Reset the device
dm9000_reset ();
// Capture dm9000
dm9000_probe ();
// MAC initialization
// Program operating register, only internal phy supported
dm9000_reg_write (DM9000_NCR, 0x0);
// TX Polling clear
dm9000_reg_write (DM9000_TCR, 0);
// Less 3Kb, 200us
dm9000_reg_write (DM9000_BPTR, BPTR_BPHW (3) | BPTR_JPT_600US);
// Flow Control: High / Low Water
dm9000_reg_write (DM9000_FCTR, FCTR_HWOT (3) | FCTR_LWOT (8));
// SH FIXME: This looks strange Flow Control!
dm9000_reg_write (DM9000_FCR, 0x0);
// Special Mode
dm9000_reg_write (DM9000_SMCR, 0);
// Clear TX status
dm9000_reg_write (DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
// Clear interrupt status
dm9000_reg_write (DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
// Fill the MAC address
for (i = 0; i <6; i ++)
dm9000_reg_write (DM9000_PAR + i, macc_addr [i]);
// Activate DM9000
dm9000_reg_write (DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
// Enable TX / RX interrupt mask
dm9000_reg_write (DM9000_IMR, IMR_PAR);
}
2.4 DM9000 send function
void dm9000_tx (u8 * data, u32 length)
{
u32 i;
// Disable interrupts
dm9000_reg_write (DM9000_IMR, 0x80);
// Write the length of the transmission data
dm9000_reg_write (DM9000_TXPLL, length & 0xff);
dm9000_reg_write (DM9000_TXPLH, (length >> 8) & 0xff);
// Write data to be transmitted
DM_ADD = DM9000_MWCMD;
for (i = 0; i
{
DM_DAT = data [i] | (data [i + 1] << 8);
}
// Start sending
dm9000_reg_write (DM9000_TCR, TCR_TXREQ);
// Wait for the end of transmission
while (1)
{
u8 status;
status = dm9000_reg_read (DM9000_TCR);
if ((status & 0x01) == 0x00)
break;
}
// Clear To Send status
dm9000_reg_write (DM9000_NSR, 0x2c);
// Interrupt enable recovery
dm9000_reg_write (DM9000_IMR, 0x81);
}
2.5 DM9000 receiver function
#define PTK_MAX_LEN 1522
u32 dm9000_rx (u8 * data)
{
u8 status, len;
u16 tmp;
u32 i;
// Determine whether the interrupt is generated and cleared
if (dm9000_reg_read (DM9000_ISR) & 0x01)
dm9000_reg_write (DM9000_ISR, 0x01);
else
return 0;
// Read empty
dm9000_reg_read (DM9000_MRCMDX);
// Read status
status = dm9000_reg_read (DM9000_MRCMD);
// Read packet length
len = DM_DAT;
// Read packet data
if (len
{
for (i = 0; i
{
tmp = DM_DAT;
data [i] = tmp & 0x0ff;
data [i + 1] = (tmp >> 8) & 0x0ff;
}
}
} |
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