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Want to know what modifications principle DM9000 transplant, we analyzed the timing diagram and pin connections
First look at the DM9000 pin and pin connections MINI2440
DM9000 MINI2440 Functional Description
SD0 DATA0 data signal
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SD15 DATA15 data signal
CMD ADDR2 identified as address or data
Interrupt INT EINT7
IOR # nOE read enable command
IOW # nWE write enable command
AEN nGCS4 Chip Enable
It can be seen connected to 16 data lines, an address line, and that only one address line for determining the data transmission line is an address or data, so this 16 data lines for data and address multiplexing
The chip select signals used BANK4, then visit 0x2000 0000 - will activate the chip select this range when 0x27FF FFFF address enable signal nGCS4
The kernel MINI2440 provided, DM9000 address IO address 0x2000 0000, the data IO to 0x2000 0004
IO write data to the address will not be activated when ADDR2, so the data is transferred to the DM9000 address, and write data to the data IO when activated ADDR2, so as to transmit data DM9000 data
Now look DM9000 and S3C2440 timing signal
DM9000 timing of the write
IO16, IO32 these two pins and is not connected MINI2440, so I do not see these two pins timing
There is a write command after enabling the end of the next write command to enable the required minimum of 84ns intervals for T6
Then S3C2440 write timing, since the DM9000 is connected to the BANK4, and BANK write sequence is as follows
Since the DM9000 on MINI2440 only chip enable and write enable command and data signals, so we do not see and nBE ADDR signal, then what are summarized as follows
How many of these do what is it? ~
Take a look BANKCON4
Here the value of the clock cycle, while BANKCON is connected to the Memory Controller (refer to data sheet S3C2440A Table 1-4), and Memory Controller using Hclk bus clock signal (refer to Figure 7-1 S3C2440A data sheet, thanks for pointing kasim greatly), according to S3C2440 manual, Hclk Fclk by dividing down the specific division different than that of each of the board settings, so here frequency set according to the board to set their own analysis, assuming that the frequency is 400MHz, then Fclk, Hclk, Pclk dividing ratio of 1: 2: 4, it is what Hclk 200MHz, do it every clock cycle is 5ns
DM9000 and start a timing diagram comparing the calculated
Tcos correspond to T1, then it must be a minimum of 5ns, which is a clock
Tacc corresponding to T2, then it must be a minimum of 22ns, it happened here, what we have to choose six clock, that is 30ns
Toch corresponding to T5, where no set, but according to the literal meaning, I think Tcoh is Toch, Toch least should be 5ns, which is a clock
Tcah correspond T4, it has been due before the Toch, and do it where you can set 0ns, namely 0 clock
In the S3C2440, the end of a write command to enable the next write command to enable the start of the interval is Toch + Tcah + Tacp + Tacs + Tcos
Tacs after starting address signal interval chip select signals, we are here to set 0ns, namely 0 clock
Toch + Tcah + Tacp + Tacs + Tcos should be> 84
5 + 0 + Tacp + 0 + 5> 84
Tacp> 74
However, the maximum Tacp for 6 clock, that is 30ns, 44ns also less, about 9 clock
Just modify Toch Tcah Tacs and Tcos, although we give are the minimum, but in order to signal stability, its scope can be relaxed,
The Tcos and Toch set to 4 clock
The Tacs and Tcah set to 2 Clock
So the total time (4 + 2 + 6 + 2 +4) * 5 = 90ns
Finally DM9000 1 cycle can only handle one data, the PMC should be normal (1data)
Write timing analysis done, and now look at the read timing
DM9000 read timing as follows
What summarized as follows:
Read command after enabling the end of a read command to the next enabled require a minimum of 80ns intervals for T6
Then S3C2440 read timing, timing is as follows
Tcos correspond to T1, then it must be a minimum of 5ns, which is a clock, set here and write the same four clock
Tacc corresponding to T2, then it must be a minimum of 22ns, and here is set to write the same six clock
Toch corresponding to T5, then it must be a minimum of 5ns, which is a clock, set here and write the same four clock
Other interval to set and write the same
Tcah to two clock
Tacp six clock
Tacs for the two clock
PMC is normal (1data)
Then look at the meet after enabling the read command to the end of the next read command to enable intervals not 80ns
Or Toch + Tcah + Tacp + Tacs + Tcos
(4 + 1 + 6 + 1 + 4) * 5 = 15 * 5 = 90ns, can qualify
What do BANKCON4 settings are as follows
Tacs = 2 Ge clock = 10
Tcos = 4 Ge clock = 11
Tacc = 6 Ge clock = 100
Tcoh = 4 Ge clock = 11
Tcah = 2 Ge clock = 10
Tacp = 6 Ge clock = 11
PMC = normal (1data) = 00
That is 0x5CEC
Look BWSCON, this register is responsible for configuring BANK bandwidth and wait state
We are for the nGCS4, it mainly depends on what ST4, WS4 and DW4 these fields
DW4 described as BANK4 bandwidth, DM9000 took 16 address lines, then it is the bandwidth of 16, where the election 01
Description WS4 is whether BANK4 a wait state, DM9000 WAIT pin is not connected, it is possible regardless of the field
Description ST4 is whether BANK4 use UB / LB (write high / low byte enable), DM9000 not connected nWBE [3: 0] These four pins, so regardless of the field |
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