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  See how --nand flash timing diagram of a read operation Comments
  Add Date : 2018-11-21      
  This article describes the physical structure is not nand flash and some basic knowledge about the nand flash. You need to at least understand the physical structure of your hands nand flash, and some, such as read and write commands

Impression about the operation, you need at least read s3c2440 regarding nand flash control register instructions.

Because I have no special knowledge learned in this regard, the following description is the voice of experience.

Here I use K9F2G08-SCB0 to introduce this nand flash read timing diagram. Different chip operation timing may be different, the read command will have some differences.

Of course, in fact, sometimes like nand flash integrated peripherals such s3c2440 his controller. Specific details of the timing of the read and write operations (such as CLE / ALE setup time, the write pulse width data to establish and hold time, etc.), do not understand the early is not much problem.

Because s3c2440 internal nand flash controllers do most of the work, you need to do is to set some basic time parameters only. Then nand flash automatically operate these details.

Of course, if there is no integrated nand flash on the processor controller must be so long to write their own timing the operation. So understanding the bottom of the timing of the operation is always good

However, the upper point, such as read and write operations of the step sequence (such as a read operation, you have to chip enable, and then send the command, and then send the address, if necessary need to send a command, and then need to wait for the operation to complete before reading data ).

It is necessary to understand. It does not understand, how it carried out the operation of the device

That s3c2440 can say that after you set the time very few parameters, each a step in the minor operations are done for you. (Such as a write command, you just write a command to the appropriate registers, cpu inside each pin will be co-issued

Adapted to achieve the write command signal operation).

And we need to do is to write about these commands, write the address, wait for the operation to complete. And other steps together. Thereby completing a read operation

As I said above, although we do not need to write each step of the most subtle timing. But to understand the next. Let you low-level details of each step is more apparent

First look at a command latch timing. That is above that read nand flash operation is not a write command step it. Well, this is how to achieve concrete step.

First, we definitely have to chip select nand flash. Only the selected chip to make him work ah

nand flash is via ALE / CLE (active high) to distinguish data on the line command (CLE valid), address (ALE valid) or data (CLE / ALE are not valid).

Since this is a write command then it must CLE active (high) ALE invalid (low).

Since the same command is written nand flash so there must be a write cycle. We need to note is written in the rising edge or falling edge.

1 Here is the command latch is timing, then we should pay attention to the fact that only CLE high during this period of timing. (Write command ah, CLE is active (high level) indicates the current data actually commands) ALE is low at this time and we certainly do not care about him

2 Therefore, CLE low period, all shades of gray on most of the other pins, which means we do not care about this period the level of these pins

3 then this is when data is read nand flash to it, noting the rising edge of a signal nWE all other pin through the timing of the vertical bar (which seems to be called lifeline? I do not know)

       This is the explanation, the write data (command data is ah, can only effectively be distinguished by CLE) is valid on the rising edge of WE.

       That is, although WE is active low, but not to say WE becomes a low level, the command is latched (ie really get command) but the rising edge of WE, the command really is locked deposit.

Know the above three points, we will know a rough, then the rest of the figure are only those txx label. It clearly refers to the time, but specifically refers to what time yet.

Refers to the time is referred to the arrows on both sides between the two vertical lines. (In each signal transition edge, has a small vertical line)

The rest is in the end is what these times represent. There is nothing difficult, I feel new to read. Because we never had before. (As when the microcontroller is not just learning to understand the various reasons why we never come into contact).
These times numerals in front of the data sheet has a description

For example tCLS tCLH from the data sheet we can see the points table represents the CLE setup time, hold time and CLE signal.

Simple point you can understand, I let CLE pin has gotta give the world some time to become a high bar. It can not instantly becomes a high level

But from the timing chart we can see more clues before is not said on the rising edge of WE not have a longest vertical line through the other signal lines do. We say he instructed, and data (also command data)

       Is latched on the rising edge, the rising edge of WE, I wrote the command data on the line really is latched (received), but we note that the rising edge of WE CLE signal before it has a valid.

       So we say, before the real command data is latched, CLE effective period of time is called tCLS CLE signal settling time.

      WE after rising edge. Command has been accepted, but when the CLE can actually become invalid, as it has acquired the command

       But he did not end immediately, but only after the end of Tclh time. Then we say that time is tCLH CLE hold time.

Then again according to instructions in the manual indicates tCS chip select signal settling time, tCH represents chip select signal hold time

      tDS represents data setup time, tDH represents data hold time

We see here a small law, the data sheet S to the end of time generally refers to the settling time in H ending time is the holding time



Here the command-latch timing analysis will be finished. We look at the address latch timing diagram, this figure a bit complicated,

Because the characteristics of nand flash is the address cycle usually takes several, several times that an address is sent

Then give the data sheet corresponding time label instructions

We follow the same steps above analysis

1 Here is the address latch is timing, then we should pay attention to the fact that only ALE high during this period of timing. (Write command ah, when ALE is active (high level) indicates the current data actually address) CLE certain at this time is low, you can not control

2 Therefore, ALE is low periods, are shades of gray on most of the other pins, which means we do not care about this period the level of these pins

WE have the same 3 rising through a long vertical line of the other signals, which is representative of data (in fact, here is the address) is latched on the rising edge

Then the rest, whether you understand

tCLS that we do not care, because they are fundamentally CLE invalid.

tCS As previously analyzed, it refers to the chip select signal CE at the effective time of the rising edge of WE is latched address before, which is CE Setup Time

tWC it? Do not know? I do not know look at the manual ah, in front of the label also said that these times will be given in the manual.

       From the explanation above, we see the manual, it refers to a write cycle time

tWP write pulse width (that is, WE are low limited, twp refers to the duration of the low level is effective time)

tWH easy to understand, that is high time

ALS is not this address signal ALE setup time thing

ALH ALE signal is valid hold time ah

TDS TDH data setup and hold time

Like on the face of the command timing analysis, setup and hold times where the signal that your data is latched demarcation point (WE rising edge)

See here who believe that a closer look should see approximately how a timing diagram, but here we are involved nothing more than some of the above setup / hold time.

Complex point of it.

Here's a look at a more complex timing chart, in fact, is not complicated, mainly explain how you can not look at the manual to know what is meant by the time txx




This sequence is not complicated, but he is not so are some of the setup and hold time image analysis above. Here comes with more than a label

But as said earlier. See the manual! Manual has a description for each time parameter. But even Beginners usually look at the manual, these time parameters also do not know what that means.

Here we see the previous manual, the first under his own analysis. Method, the manual has become something to verify your wrong, and not something you find answers.
TRC This parameter is a bit simple. Look at his range is a RE-cycle time, then just in front of the tWC it should be the same. Then it is supposed to represent a period of time RE signal (read signal of a cycle)

TREA it? See why they can not see the label, then we see him start and end time from the timing diagram can be seen, this is the time from RE active (low) to the time of its occurrence between.

So tREA imagine it should be read into the data valid signal is read between the Time

We are behind this same analysis

For example, that last tRHZ from RE inactive (high level) to the data line into a high impedance state between the time (data line drawn in the middle represents the high-impedance state)

Look in the manual to explain basically what it means

Here to see how the timing diagram, I believe we should be able to understand. Possibly even without looking at the manual, you know what he meant. Because we from time to time starting address to guess the meaning of the label

The above analysis, it is the underlying operations are, if we use this advanced processor s3c2440 timing of these operations we do not need to achieve, at most, a few go out into the register

Set about for some time and then said above, CPU in nand flash controller will automatically complete all of the above operations. But also need to understand the reason for this is that if you do not get a

nand flash controller processor how to do it yourself you can only achieve these specific write command, write address. Etc. unit operation.

These unit operations can then be combined into a read data, write data and other operations (such as mentioned above, he is not read a simple command but a series of operations, you have to chip enable, and then send a command (read command),

And then send the address (the address of the data to be read), if required, the need to send a command, and then need to wait for the operation to complete, and then reading the data)

Having these specific unit operations, we look at a specific read what steps need. That is, we need to really have to master the timing of the operation

For me this nand flash read operation sequence is as follows

We should pay attention to the bottom line that is mainly I / Ox signal line state, which he indicates a read operation, unit step needed.

1 First, we see what a 0x00 yes? data? address? command? See ALE / CLE line ah, the two lines is not determined the type of data now Well

       Down looking up, we know that the data is 0x00 in CLE effective period then it is a command

2 then the address (5Cycle) address sequence that is five (when this nand flash read data address specified sequence of addresses to send five), looking up, the data in the ALE effective period, it should be the address of the

       (For these five addresses, the first two is the column address, the row address is three behind in the physical structure of nand flash row address corresponding to a page, the column address corresponds in a column on this page)

3 Then came the 0x30, CLE effective at this time, it is commanded (that is to say this nand flash read operation requires two commands).

       But immediately after the data has not come out, we saw in the DATA Output data output that is still some time before, why this time?

       Looking up R / nB This explains why the data line, this time it is low for the indication now is busy, not ready for data output. Why is this so?

       Because you write a command to write the address of the data to be read, and write a command. Cpu always give you some time to deal with these commands it,

       R / nB is low at this time is to deal with these commands (in fact, according to the command that you locate a data read internal registers),

       And other R / nB goes high, and instructs the command processing is completed, the data will now be read out.

We sum up the manual we will know the specific steps a read operation,

1 is a first nand flash peripherals, to access he needs to chip select it, so before you perform the steps required on the timing chart chip select nand flash.

2 Looking back is to install a timing diagram to see timing diagram! The first step, first send a command 0x00.

3 See timing diagram! Then send five address sequence (first column address to send two, sending three row address (ie page address))

4 see timing diagram! Followed by a command 0x30.

5 see timing diagram! R / nB pin LOW busy now, these commands being processed, it would have to wait for the R / nB pin goes high

6 see timing diagram! This time you can read the data

7 the end of a read operation nand flash temporarily need to use, then do not forget to chip select signals should be canceled.

As each of these steps in a specific sequence, cpu in nand flash controller will help us complete. Several times we have to do is to set the parameters

Here we have repeatedly stressed to see the timing diagram. In fact, the pre-school for embedded data sheet, have to look back to see more you know, look at what you focus on, what is your program and you do not care regardless of an operation. So later you can, get a peripheral can write his operations. Rather than follow the book back step. As long as the Manual on the line.

The above step is a concrete step of the read operation, but before using a device we need to initialize it once. As for initialization is set above us several times mentioned

We said s3c2440 has helped me do a lot of the underlying unit operations, we simply set several time parameters nand flash chip timing operation will automatically send the appropriate action

So in the end we set up a few times.

On s3c2440 manual gives several parameters we need to set.




We can see that the first one is a timing diagram of the command and address latch timing, the second web is the timing of data read and write.
As can be seen, the time they want to set is the same. Previously analyzed so much, it should not be difficult to see here

1 TACLS very clear representation of the time is to establish CLE / ALE (here is not accurate, in fact, CLE / ALE WE become effective until the time between a low level, but WE is latched on the rising edge only command / address )

WE 2 TWRPH0 represents the pulse width, i.e. the effective time

3 TWRPH1 represents CLE / ALE hold time

That in the end what is set to digital yet. Since the image above read / write time parameter / command / address operational needs are the same

So we just look for a command from the nand flash in sequence to control not on the list

Take the above we said command latch timing to compare

Then we can get the following relationship




Then how much to set it? The minimum time to read the manual ah, manuals for tWP tCLH tCLS will at least give the required

The chip nand flash manual three parameters requirements


So TWRPH0 = tWP> = 12ns

       TWRPH1 = tCLH> = 5ns

       TACLS = tCLS - tWP> = 0;

These three parameters as described in the data sheet s3c2440


Of course there is a time in HCLK as a unit, these parameters are nand flash control register set NFCONF

So here I am useless use MPLL HCLK is 12MHZ

So TWRPH0 = 0 TWRPH1 = 0 TACLS = 0; (if your clock frequency is relatively high, it would have to set up a number of other of course is that you really do not know the total right to set the big points, but the speed may be. slower.)

       So NFCONF = 0; (NOFCONF other bits in the data sheet described here simply read other bits may not be provided)

Then click initialize ECC enabled nand flash controller (we just set up a few time parameters, the specific timing of the operation is done by him, so he can make)

Then you need to remove the chip select nand flash because we do not currently have to operate it, ah, just initialize it. It still should be canceled chip select, read and other real time and then enable the chip select signals

NFCONT = (1 << 4) | (1 << 1) (1 << 0);

(Data sheet has a corresponding bit instructions)

Finally, the first use nand flash we need to reset it.

In summary, the following initialization code nand flash

void nand_init (void) {

        NFCONF = 0;

        NFCONT = (1 << 4) | (1 << 1) | (1 << 0);

        nand_reset (); // nand reset code behind


Here is some code written address associated with nand flash models. Need to refer to specific chip Guide


void select_chip (void) {

        NFCONT & = (~ (1 << 1));

        int i;

        for (i = 10; i> 0; i--);


void deselect_chip (void) {

        NFCONT | = (1 << 1);

        int i;

        for (i = 10; i> 0; i--);


void write_command (unsigned char command) {

        NFCMMD = command;

        int i;

        for (i = 10; i> 0; i--);


/ *

       The nand flash page size is 2K

       Five address cycles (2 and 3 column address and the row address (page address))

* /

void write_address (unsigned int address) {

        unsigned int page = address / 2048;

        unsigned int col = address & 2048;

        int i;

        NFADDR = col & 0xff;

        for (i = 5; i> 0; i--);

        NFADDR = (col >> 8) & 0x0f;

        for (i = 5; i> 0; i--);

        NFADDR = page & 0xff;

        for (i = 5; i> 0; i--);

        NFADDR = (page >> 8) & 0xff;

        for (i = 5; i> 0; i--);

        NFADDR = (page >> 16) & 0x01;

        for (i = 5; i> 0; i--);


unsigned char read_one_data (void) {

        return NFDATA;

        int i;

        for (i = 10; i> 0; i--);


void wait_ready (void) {

        while (! (NFSTAT & 1));

        int i;

        for (i = 10; i> 0; i--);


static void nand_reset (void) {

        select_chip ();

        write_command (0xff);

        wait_ready ();

        deselect_chip ();


void nand_init (void) {

        NFCONF = 0;

        NFCONT = (1 << 4) | (1 << 1) | (1 << 0);

        nand_reset ();


/ *

nand flash read operation is in units of pages.

 des: nand flash data read out into what

 start_addr: Where to start reading

 size: how to read

* /

void nand_read (unsigned char * des, unsigned int start_addr, unsigned int size) {

        unsigned int col = start_addr & 2048;

        select_chip ();

        unsigned int start = start_addr;

        unsigned int end = start_addr + size;

        while (start
               write_command (0x00);

                write_address (start);

                write_command (0x30);

                wait_ready ();

                while ((col <2048) && (start
                        * Des = read_one_data ();

                        des ++;

                        col ++;

                        start ++;


                col = 0;


        deselect_chip ();

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